12.1 DC Electrical Specification
DC Input/Output Specifications
All processor output drivers are CMOS push-pull, and the signals swing between VccQ and Vss. In open drain mode, the gates of the PMOS pullup devices are disabled. Input-only pins include a disabled output buffer for implicit ESD protection.
Tables 12-2 and 12-3 describe the DC characteristics of the I/O signals for the HSTL and CMOS/TLL configurations.
NOTE: As the JEDEC Standard 8-x evolves, the HSTL specifications will also change, and the processor will remain compliant with these standards.
Table 12-2 DC Characteristics for HSTL Configuration
Table 12-3 DC Characteristics for CMOS/TTL Configuration
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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